Description

You will execute analog and mixed-signal layout designs for advanced CMOS technologies, owning the process from floorplanning to physical verification.

Responsibilities

• Own the layout process including floorplanning, placement, routing, and physical verification.
• Collaborate with circuit designers to meet specific design requirements and specifications.
• Manage physical verification checks including DRC, LVS, DFM, ERC, EM, and IR.
• Apply standard analog layout techniques while addressing deep sub-micron challenges.
• Address reliability physics concerns such as EM, ESD, crosstalk, shielding, and latchup.

Required Skills

• 5 to 8 years of experience in CMOS analog and mixed-signal layout.
• Proven expertise with FinFET layouts and nodes at 28nm, 14nm, 7nm, and 5nm.
• Hands-on experience with Virtuoso (L/XL/GXL), Calibre, StarRC, and Totem.
• Experience designing analog mixed-signal blocks such as PLL, SerDes Phy, ADC, DAC, Oscillators, and LDOs.
• Strong understanding of matching constraints and design-driven constraints.
• Proficiency in Design Rule Checking (DRC) and Layout Versus Schematic (LVS).
• Knowledge of Design for Manufacturing (DFM) and electrical aspects of layout.

Preferred Skills

• Experience with IO Ring and Testchip design.
• Exposure to automated place and route tools like ICC or SOC Encounter.

Key Skills

Education

Any Graduate