Description

Drive pre-silicon and post-silicon data analytics, visualization, and modeling for next-generation hardware products.

Responsibilities

• Implement new methodologies for chip quality improvement, including advanced fault modeling and Silicon Lifecycle Management.
• Solve complex Design For Test problems using algorithm design, statistical analysis, and Applied AI methods.
• Develop and deploy DFT methodologies and explore LLM-based solutions for test design.
• Mentor junior engineers on test designs, cost considerations, and quality trade-offs.
• Partner with multi-functional teams to bridge data insights with hardware implementation.

Required Skills

• 8+ years of experience with a BSEE (or 6+ years with MSEE / 4+ years with PhD).
• Deep understanding of DFT fundamentals, including fault modeling, ATPG, and fault simulation.
• Proficiency in statistical tools for analyzing and interpreting complex datasets.
• Strong programming and scripting skills in Python, Perl, or C++.
• Exposure to RTL & clocks design, STA, place-and-route, and power.
• Experience with Silicon debug and bring-up on ATE or SLT platforms.
• Background in low-power DFT, Data Visualization, Applied Machine Learning, or Database Management.

Preferred Skills

• Experience in advanced fault models and Silicon Data Corruption.
• Background in applying AI to EDA-related problem-solving.

Key Skills

Education

Bachelor’s Degree