Description

You will develop memory Fast Cache instances for next-generation Arm Cores to achieve target PPA.

Responsibilities

• Develop memory Fast Cache instances for next-generation Arm Cores.
• Optimize designs for Power, Performance, and Area (PPA) trade-offs.
• Perform margin analysis, characterization, and verification.
• Implement high-speed, low-power CMOS circuit designs and clocking schemes.

Required Skills

• 5+ years of experience in SRAM/memory designs.
• Expertise in CMOS circuit design, including static, dynamic, and complex logic circuits.
• Experience with margin analysis and characterization.
• Ability to understand FE (Front end) models and Verilog.
• Deep understanding of Power vs. Performance vs. Area trade-offs in CMOS design.
• Degree in Electronic Engineering.

Preferred Skills

• Scripting experience with Perl, Tcl, or Python.
• Experience with Cadence or Synopsys flows.
• Experience in circuit simulation, standard cell optimization, silicon validation, and debug.

Key Skills

Education

Any Graduate