Description

Own micro-architecture and RTL development of design modules to meet performance, power, and area requirements.

This role is on-site.

Responsibilities

• Define critical features in collaboration with hardware architects.
• Verify implementation correctness by working with verification teams.
• Ensure designs meet timing, interface, and routability requirements with timing, VLSI, and physical design teams.
• Prototype designs with FPGA and software teams to validate software functionality.
• Conduct post-silicon verification and debug.

Required Skills

• 4+ years of experience in micro-architecture and RTL development for complex designs.
• Expertise in Verilog.
• Deep understanding of the ASIC design flow, including RTL design, verification, logic synthesis, prototyping, timing analysis, floor-planning, ECO, and lab debug.
• Experience with design and verification tools such as VCS, Debussy, or GDB.
• BS or MS degree in Engineering or equivalent experience.
• Proficiency in Python, Perl, or Shell scripting.

Preferred Skills

• Design experience in memory subsystems or network interconnect IP.

Key Skills

Education

Any Gradute