Description

You will verify complex IP modules and SoC-level components for pre-silicon validation. You own the full verification lifecycle, from test plan creation to coverage closure.

Responsibilities

• Develop and implement UVM-based SystemVerilog testbenches and simulation environments.
• Create assertion checkers, coverage monitors, and low-power simulation setups using UPF.
• Develop C/Assembly diagnostics and analyze coverage data to debug simulation failures.
• Verify AMBA protocols, Bluetooth MAC, and Wi-Fi 802.11 MAC implementations.
• Collaborate with cross-functional teams to bring up features and close verification gaps.

Required Skills

• 8+ years of hands-on design verification experience with IP blocks and SoCs.
• Expertise in SystemVerilog, SVA, and UVM methodology.
• Strong knowledge of Verilog and computer architecture fundamentals.
• Proficiency in scripting languages such as Perl or Unix Shell.
• Hands-on experience with industry-standard EDA simulation tools.
• Experience with low-power simulation, UPF setup, and debugging LP issues.
• Background in AMBA protocols, Bluetooth MAC, or Wi-Fi 802.11 MAC.
• MS or higher in EE/EC/ECC Engineering.

Key Skills

Education

Any Graduate