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Senior Design Verification Engineer

CodersBrain

 

Bangalore, Karnataka, India

Posted On: Just posted
Experience: 5+ years
Availability: Hybrid
Openings: 1
Category: Senior Design Verification Engineer
Tenure: Full-time Only
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Description

Required Qualifications & Skills

  • Education: B.Tech / M.Tech in Electronics, VLSI, Computer Engineering, or related fields.
  • Experience: 5+ total years in ASIC/SoC Design Verification, with at least 2+ years dedicated to CPU verification (RISC-V, ARM, x86, or custom cores).
  • Languages & Frameworks: SystemVerilog, UVM, Assembly (RISC-V/ARM), C/C++, and Python/Perl/TCL scripting.
  • Computer Architecture: Deep understanding of CPU pipeline execution, out-of-order concepts, cache coherency, memory ordering, and interrupts/exceptions.
  • EDA Simulators: Hands-on experience with Synopsys VCS, Cadence Xcelium, or Siemens Questa.
  • Protocols: Strong exposure to AMBA protocols (AXI/AHB/ACE/CHI).

Preferred Qualifications

  • Knowledge of power-aware verification (UPF/CPF).
  • Exposure to high-speed interconnect protocols (PCIe, CXL, DDR).
  • Familiarity with hardware emulation platforms (Palladium, Veloce, Zebu) or post-silicon validation flows

Education

Bachelor's degree

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