Senior Design Verification Engineer

You will drive the full verification cycle for IP, sub-systems, and SoC level designs.

Responsibilities

• Define and implement IP/SoC verification plans.
• Build verification test benches to enable IP, sub-system, and SoC level verification.
• Develop functional tests based on the verification test plan.
• Drive design verification to closure using defined functional and code coverage metrics.
• Debug, root-cause, and resolve functional failures in partnership with the design team.

Required Skills

• 5+ years of hands-on experience in SystemVerilog/UVM methodology.
• Experience with C/C++ based verification.
• Proven ability to develop UVM-based verification environments from scratch.
• Experience architecting and implementing Design Verification infrastructure.
• Experience verifying ARM/RISC-V based CPU sub-systems or SoCs.
• Expertise in protocols such as AMBA, PCIe, DDR, USB, or Ethernet.
• Proficiency in EDA tools and scripting using Python, TCL, Perl, or Shell.
• Experience with revision control systems like Git, SVN, or Mercurial (Hg).
• Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience.