Description

You will drive functional verification processes for ASIC designs. You own the verification plan, simulation environment, and debugging efforts.

Responsibilities

• Develop and execute verification plans using UVM or OVM methodologies.
• Build and maintain simulation environments to validate RTL code.
• Debug complex design issues within Verilog or VHDL environments.
• Automate verification tasks using scripting languages.
• Collaborate with the design team to ensure protocol compliance for interfaces like PCIe, USB, Ethernet, or DDR.

Required Skills

• 3+ years of hands-on experience in design verification.
• Proficiency with Universal Verification Methodology (UVM) or OVM.
• Experience with industry-standard tools such as Questa, VCS, or ModelSim.
• Strong understanding of RTL coding using Verilog or VHDL.
• Solid knowledge of Application-Specific Integrated Circuits (ASIC).
• Experience with DDR3 SDRAM or similar industry-standard protocols.
• Proficiency in Python, Perl, or TCL for automation.
• Strong debugging and problem-solving capabilities.

Preferred Skills

• Any Graduate degree.

Key Skills

Education

Any Graduate