Description

You will own the full verification cycle for IP, sub-systems, and SoC level designs, driving efforts from plan definition through closure.

This role is on-site.

Responsibilities

• Define and implement verification plans for IP and SoC designs.
• Build UVM-based verification environments and test benches from scratch.
• Develop functional tests aligned with verification plans and coverage metrics.
• Debug, root-cause, and resolve functional failures in partnership with design teams.
• Drive design verification to closure using defined functional and code coverage goals.

Required Skills

• 5+ years of hands-on experience in SystemVerilog and UVM methodology.
• Proven ability to architect and implement verification infrastructure.
• Experience with C/C++ based verification tasks.
• Background in verifying ARM or RISC-V based CPU sub-systems or SoCs.
• Expertise in protocols such as AMBA, PCIe, DDR, USB, or Ethernet.
• Proficiency in scripting using Python, TCL, Perl, or Shell.
• Experience with revision control systems like Git, SVN, or Mercurial.
• Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience.

Key Skills

Education

Any Graduate