Description

You will drive functional verification for complex processor architectures and digital designs.

Responsibilities

• Develop and maintain functional verification tests using UVM at the subsystem level.
• Build testbench components to support next-generation IP.
• Maintain and improve current test libraries for IP-level testing.
• Act as technical lead for IPs in Control Fabric.
• Provide technical support to cross-functional teams across different sites and time zones.

Required Skills

• 6+ years of experience in Design Verification.
• Proficiency with SystemVerilog and UVM.
• Experience with AXI protocol and Bootcode Verification.
• Strong knowledge of C and C++.
• Experience with Functional Verification methodologies.
• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Key Skills

Education

Any Graduate