Description

You will lead functional verification for next-generation IP and subsystem components, ensuring robust test coverage and protocol compliance.

This role is on-site.

Responsibilities

• Develop and maintain functional verification tests using UVM at the subsystem level.
• Build testbench components to support the development of next-generation IP.
• Maintain and improve existing test libraries for IP-level testing.
• Lead technical verification efforts for IPs within the Control Fabric.
• Provide technical support to cross-functional engineering teams.

Required Skills

• 5+ years of experience in design verification.
• Proficiency in SystemVerilog (SV) and UVM.
• Strong programming skills in C and C++.
• Experience with AXI protocol and Bootcode Verification.
• Scripting proficiency in Perl, Ruby, and Makefile.
• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Key Skills

Education

Any Graduate