Description

Lead the end-to-end verification cycle for complex designs from remote locations within the USA.

Responsibilities

• Develop comprehensive test plans and implement BFM, Driver, Monitor, and Scoreboard components within the testbench.
• Execute stress and corner testing, gate-level simulations, and assertion-based verification.
• Drive verification closure through rigorous debugging and coverage analysis.
• Report daily or weekly technical progress directly to customers.

Required Skills

• 10 to 15 years of experience in SystemVerilog HVL and C/C++.
• 10+ years of hands-on experience with UVM.
• Proficiency in SVTB, UVM, and C++ testbench environments.
• Strong skills in debug and assertion coding.
• Experience with scripting languages including Perl, Python, or Make.
• Ability to manage the complete verification lifecycle and achieve coverage closure.
• Any protocol experience.

Preferred Skills

• Understanding of DSP principles.
• Experience using Subversion for repository management and Bugzilla for tracking.

Key Skills

Education

Any graduate