Description

You will define and implement DFT architecture for SoC and ASIC designs, owning the strategy from RTL through silicon bring-up.

This role is on-site.

Responsibilities

• Define and implement DFT architecture for SoC/ASIC designs.
• Develop and integrate scan, MBIST, LBIST, boundary scan, and ATPG solutions.
• Own DFT strategy from RTL to silicon, covering test planning, insertion, simulation, and verification.
• Support test pattern generation and bring-up at ATE.
• Debug DFT-related silicon issues and support production ramp.

Required Skills

• Strong understanding of DFT concepts including scan, boundary scan (JTAG/IEEE 1149.x), MBIST, and LBIST.
• Hands-on experience with tools like Tessent, Modus, Dft Advisor, FastScan, or TestKompress.
• Proficiency in scripting languages: Tcl, Perl, and Python for flow automation.
• Experience handling DFT for complex SoCs in 7nm/5nm/FinFET technologies.
• Familiarity with STA, synthesis, and physical design implications of DFT.
• Experience with ATE pattern generation and debug (Advantest or Teradyne preferred).
• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related field.

Key Skills

Education

Any Gradute