Description

You will lead design-for-testability efforts to ensure high test coverage and pattern quality.

Responsibilities

• Execute Scan and ATPG flows to achieve target coverage.
• Apply coverage improvement techniques for stuck-at, transition, delay, bridging, and IDDQ faults.
• Perform ATPG simulations using SDF to validate patterns.
• Debug Tester/ATE patterns and hardware-related issues.
• Develop automation scripts to streamline DFT workflows.

Required Skills

• 4+ years of relevant experience in DFT.
• Proficiency with Cadence Modus, Synopsys DFTMax/TetraMax, or Mentor/Tessent tools.
• Strong expertise in Scan and ATPG methodologies.
• Experience with Stuck-at, Transition, Delay, Bridging, and IDDQ fault models.
• Ability to perform ATPG simulation with SDF.
• Advanced debugging skills for complex design issues.
• Scripting proficiency in TCL, Shell, Perl, or Python.
• Understanding of JTAG and low-power design principles.
• Background in circuit design and computer simulations.

Preferred Skills

• Experience with ATE pattern debugging.

Key Skills

Education

Any Graduate