Description

You will develop and implement Design for Testability solutions for complex silicon architectures.

Responsibilities

• Develop DFT architectures and methodologies including Scan, ATPG, MBIST, and JTAG.
• Implement test patterns and methodologies using industry-standard toolsets.
• Write automation scripts to streamline DFT flows and workflows.
• Collaborate with cross-functional teams across different geographies to ensure design integration.

Required Skills

• 5 to 12 years of relevant experience in DFT engineering.
• Proficiency in Scan, ATPG, MBIST, and JTAG architectures.
• Hands-on experience with Cadence, Synopsys, or Mentor DFT tools.
• Strong scripting skills in Python, Perl, or TCL.
• Bachelor’s Degree in a relevant engineering field.
• Ability to communicate effectively within global, cross-functional teams.

Key Skills

Education

Bachelor’s Degree