Senior DFT Engineer

KEY RESPONSIBILITIES

• Partner closely with RTL design teams to define, review and ensure correct insertion of DFT architectures across SoC and IP designs.

• Develop, implement and verify robust DFT schemes for hard IPs and FPGA-based designs.

• Own test development for digital logic using scan compression and multiple fault models, including stuck-at, transition and path-delay.

• Develop and validate MBIST architectures and patterns to ensure high coverage and production readiness.

• Lead debugging of scan, MBIST and pattern-related issues on bench and ATE, driving root-cause analysis and resolution.

• Collaborate with NPI, Test Engineering and Product teams to deliver high-quality, production-ready test content on schedule.

• Support diagnosis and yield improvement efforts throughout the product lifecycle.

• Design and implement firmware-driven, cost-effective test strategies with built-in diagnostic capabilities.

• Optimize test methodologies to improve coverage, reduce test cost and enhance overall product quality.

• Contribute to continuous improvement by mentoring team members and sharing best practices.

PREFERRED EXPERIENCE

• Experience designing and implementing complex, chip-level DFT architectures for advanced SoCs.

• Hands-on experience with DFT implementation, including Scan and Scan Compression, at IP and SoC levels.

• Experience using DFT and ATPG tools across stuck-at, at-speed and path-delay fault models.

• Proficiency in RTL logic design using Verilog, with working knowledge of synthesis and static timing analysis.

• Experience developing testbenches and running simulations in RTL, gate-level and SDF environments.

• Working knowledge of MBIST architectures and pattern development is preferred.

• Familiarity with FPGA design and synthesis flows is a plus.

• Exposure to post-silicon debug, bench setup and ATE-based validation is a plus.

• Comfortable working in Linux environments and using scripting languages such as Perl, Tcl or Python.

ACADEMIC CREDENTIALS

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related field is preferred.

• Formal education or training with a focus on digital design, DFT or test methodologies is desired.

• Tessent Scan, ATPG or MBIST certifications are a plus