Description

You will own the DFT architecture, implementation, and test strategy for SoC and IP designs, ensuring production-ready quality and coverage.

This role is on-site.

Responsibilities

• Partner with RTL design teams to define and review DFT architectures for SoC and IP designs.
• Develop and verify DFT schemes for hard IPs and FPGA-based designs, including scan compression and MBIST patterns.
• Own test development for digital logic using multiple fault models such as stuck-at, transition, and path-delay.
• Lead debugging of scan, MBIST, and pattern issues on bench and ATE, driving root-cause analysis.
• Collaborate with NPI and Test Engineering to deliver high-quality test content and support yield improvement efforts.

Required Skills

• 5+ years of experience in DFT implementation, including Scan and Scan Compression at IP and SoC levels.
• Proficiency in DFT and ATPG tools for stuck-at, at-speed, and path-delay fault models.
• Strong RTL logic design skills using Verilog, with working knowledge of synthesis and static timing analysis.
• Experience developing testbenches and running simulations in RTL, gate-level, and SDF environments.
• Working knowledge of MBIST architectures and pattern development.
• Proficiency in Linux environments and scripting languages such as Python, Perl, or Tcl.
• Familiarity with FPGA design and synthesis flows.
• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

Preferred Skills

• Experience designing complex, chip-level DFT architectures for advanced SoCs.
• Exposure to post-silicon debug, bench setup, and ATE-based validation.
• Tessent Scan, ATPG, or MBIST certifications.

Key Skills

Education

Bachelor's degree