Description

You will work as a Senior DV Engineer focusing on digital verification.

Responsibilities

• Verify DDR/LPDDR protocols.
• Develop and maintain verification environments using UVM.
• Lead technical efforts or manage verification teams.
• Integrate verification flows within SoC designs.

Required Skills

• 6+ years of experience in Digital Verification (DV).
• Hands-on proficiency with UVM.
• Strong experience verifying DDR and LPDDR protocols.
• Proficiency in Verilog.
• Experience working with SoC environments.
• Demonstrated experience in technical leadership or team handling.

Key Skills

Education

Not specified