Description

Key Skills: Collaboration, Communication, Data Science, Design, EDA, Go, Machine Learning, Networking, SAP, SoC, UVM

Roles & Responsibilities:

• As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SS/SoC.
• Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy.
• Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules.
• Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development.
• Senior engineers are also encouraged to support junior members.

Skills Required:

• 5-7 years of proven experience in working on IP/Subsystem Verification.
• Experienced in one or many of these technologies/ protocols - PCIe, AMBA
• Preferred Experience in PCIe Gen6 and later generations.
• Preferred Experience in RAL (Register verification).
• Good understanding in any of of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs.
• Good Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.)
• Experienced in one or more of various verification methodologies - UVM, formal and low power.
• Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support.

Nice To Have

• Possess knowledge of object-oriented programming concepts
• Practical experience of working on PCIe Sub System design.
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Education:  Bachelor's degree in Engineering

Key Skills

Education

Any Graduate