Description

Key Skills: Asic Verification, Verification, Universal Verification Methodology, Memory Interfaces (DDR4/LPDDR4), IP addressing, System Verilog

Roles and Responsibilities:

• Own ASIC verification execution for DDR/LPDDR components across block, cluster, and chip/SoC verification scopes.
• Develop and maintain UVM-based verification environments, including test bench components and reusable sequences.
• Create and refine test plans for DDR/LPDDR IP verification, ensuring thorough functional coverage and closure.
• Verify DDR controller and DDR-IO functionality, including PHY-related behaviors and integration points.
• Debug complex verification issues using SystemVerilog, analyze failures, and drive corrective actions to closure.

Skills Required:

• 10 - 15 years of relevant SoC design verification experience, including DDR/LPDDR controller/PHY and DDR-IO verification.
• ASIC verification and verification execution experience across block/cluster/chip/SoC levels.
• Universal Verification Methodology (UVM) with SystemVerilog proficiency.
• Constrained random and coverage-driven verification methodology with strong coverage closure skills.
• DDR controller and/or DDR-IO verification experience; ability to develop test bench components and DDR/LPDDR test plans.

Good to Have:

• SystemVerilog experience depth for advanced debug and verification acceleration.
• IP addressing knowledge and memory interface verification experience (DDR4/LPDDR4).
• Scripting support using Python or Perl for verification automation.

Education: BS in Computer Science/EE with 10+ years of experience or MS in Computer Science/EE with 8+ years of experience in SoC design verification

Key Skills

Education

Any Graduate