Description

Own ASIC verification execution for DDR and LPDDR components across block, cluster, and chip/SoC scopes.

This role is on-site.

Responsibilities

• Develop and maintain UVM-based verification environments, including test bench components and reusable sequences.
• Create and refine test plans for DDR/LPDDR IP verification to ensure thorough functional coverage and closure.
• Verify DDR controller and DDR-IO functionality, covering PHY-related behaviors and integration points.
• Debug complex verification issues using SystemVerilog, analyze failures, and drive corrective actions to closure.

Required Skills

• 10-15 years of SoC design verification experience.
• Deep proficiency in Universal Verification Methodology (UVM) and SystemVerilog.
• Experience with DDR/LPDDR controller/PHY and DDR-IO verification.
• Strong background in constrained random and coverage-driven verification methodologies.
• Ability to develop test bench components and DDR/LPDDR test plans.
• Experience executing verification at block, cluster, and chip levels.

Preferred Skills

• Advanced SystemVerilog skills for complex debugging and verification acceleration.
• Knowledge of IP addressing and memory interface verification (DDR4/LPDDR4).
• Scripting proficiency in Python or Perl for verification automation.

Key Skills

Education

Any Graduate