Description

You will own the verification and design of complex hardware systems.

This role is on-site.

Responsibilities

• Design hierarchical, reusable, and scalable test bench architectures using UVM and SystemVerilog.
• Develop comprehensive test plans for SOC verification targets.
• Implement verification solutions leveraging Constrained Random techniques.
• Debug and validate designs using industry-standard EDA tools.

Required Skills

• 5+ years of professional experience in digital design verification.
• Expertise in UVM and SystemVerilog for SOC verification.
• Strong background in Object-Oriented Programming (OOP).
• Proficiency in Python or Shell scripting.
• Experience with EDA verification and debugging tools.
• Familiarity with revision control systems.
• BS/MS degree in Engineering or related field.

Preferred Skills

• Familiarity with Ethernet, Mixed Signal Digital design verification, or Formal Property Verification (Jasper or similar).
• Experience with ARM Based SoC Verification.

Key Skills

Education

Any Gradute