Description

Lead validation of custom memory designs and compilers.

Responsibilities

• Verify functionality and implement fixes for design issues.
• Analyze signal integrity and propose solutions for design weaknesses.
• Run transistor-level simulations to resolve power-up or lock-up issues.
• Perform EM/IR analysis to assess timing and internal margins.
• Develop scripts to automate verification processes and data analysis.

Required Skills

• 7+ years of experience in memory design validation.
• Proficiency with SPICE, specifically HSPICE and PSpice.
• Experience using Cadence Spectre.
• Experience with Synopsys Calibre.
• Experience with Synopsys NanoSim.
• Experience with Cadence UltraSim.
• Ability to validate timing and power models through transistor-level simulations.
• Experience collaborating with design and modeling leads to execute validation plans.

Preferred Skills

• Background in silicon debugging and correlating results with SPICE models.

Key Skills

Education

Any Graduate