Description

You will be a senior engineer responsible for RTL design implementation.

Responsibilities

• Develop RTL code for ASIC and FPGA implementations ensuring optimal performance and functionality.
• Complete front end design flow from specification to RTL and netlist generation.
• Perform design micro architecture and RTL coding with proper lint and CDC analysis.
• Provide support for existing sustenance designs and maintain design documentation.
• Collaborate with hardware board design engineers for system level designs and validation.

Required Skills

• 5+ years of related experience.
• Proficiency in RTL Design.
• Experience with ASIC and FPGA.
• Strong command of Verilog and SystemVerilog.
• Solid background in Digital Design and Hardware Design.
• Familiarity with CDC (Clock Domain Crossing) analysis.
• Ability to solve complex technical problems independently.

Key Skills

Education

Any Graduate