Description

You will own the RTL design implementation for ASIC and FPGA projects, driving the front-end design flow from specification to netlist generation.

This role is on-site.

Responsibilities

• Develop and implement RTL code for ASIC and FPGA designs to ensure optimal performance and functionality.
• Execute the complete front-end design flow, including micro-architecture definition, RTL coding, linting, and CDC analysis.
• Generate netlists and provide sustenance support for existing designs while maintaining accurate design documentation.
• Collaborate with hardware board design engineers to define system-level designs and validate implementations.
• Solve complex technical problems independently throughout the design cycle.

Required Skills

• 5+ years of experience in RTL design and digital hardware implementation.
• Strong proficiency in Verilog and SystemVerilog.
• Proven experience with both ASIC and FPGA design flows.
• Solid background in Digital Design and Hardware Design principles.
• Hands-on experience with CDC (Clock Domain Crossing) analysis and static verification.
• Ability to perform design micro-architecture and translate specifications into synthesizable code.
• Strong problem-solving skills with the ability to work independently.

Preferred Skills

• Experience with system-level validation and hardware-software co-design.

Key Skills

Education

Any Graduate