Description

You will design and develop RTL for FPGA applications according to project specs.

Responsibilities

• Design and develop RTL for FPGA applications adhering to project specifications.
• Debug designs to identify and resolve issues throughout the development process.
• Validate and test FPGA functionality and performance against required standards.
• Integrate IP designs into larger systems by collaborating with cross-functional teams.

Required Skills

• 7 to 15 years of experience in FPGA RTL design and verification.
• Proficiency in Verilog and VHDL.
• Experience with SV-UVM methodology.
• Knowledge of protocols including AXI, PCIe, and Ethernet.
• Expertise using Quartus tools for synthesis, simulation, and implementation.
• Proven ability to perform board-level debugging in a lab environment.
• Experience operating lab equipment such as Logic Analyzers (LA) and Oscilloscopes (CRO).

Preferred Skills

• Experience with additional FPGA vendor toolchains.

Key Skills

Education

Any Gradute