Description

Lead the design and verification of communications and fault logging CPLD/FPGA systems within an aerospace environment.

This role is on-site.

Responsibilities

• Execute RTL synthesis, constraints design, and timing closure for complex FPGA projects.
• Develop and maintain test benches to verify RTL designs using Verilog, VHDL, or SV/UVM.
• Manage the full design lifecycle, including PHA, HDP, requirements capture, and design documentation.
• Operate within SCRUM/Sprint workflows using JIRA to track development progress.

Required Skills

• 7+ years of experience in FPGA design principles.
• 5+ years of hands-on work with Xilinx or Altera FPGAs.
• Proficiency in Verilog, VHDL, or SystemVerilog (SV/UVM).
• Experience with Cadence, Microsemi Libero, or Xilinx Vivado toolsets.
• Strong background in RTL synthesis and timing closure.
• Proven experience with DO-254 standards and aerospace industry requirements.
• Ability to perform requirements capture and technical documentation.

Key Skills

Education

Any Graduate