Description

Key Skills: RTL Design, Verilog, SystemVerilog, Data Fabric Architecture, Cache Design, Micro-architecture, Digital Design, Coherency Protocol, Memory Design, Physical Design

Good to Have Skills: Experience with Infinity Data Fabric, fabric/transport architecture, SoC requirements analysis, post silicon support, verification collaboration, and working with architects and design leads on complex technical issues.

Roles & Responsibilities:

• Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, and area targets.
• Implement digital design and micro-architecture of components of the Infinity Data Fabric, including cache design.
• Develop micro-architecture and perform RTL coding in Verilog and SystemVerilog programming languages.
• Lead design on one or more domains while managing complex technical requirements and deliverables.
• Work with architects and design leads to identify and assess complex technical issues throughout the project lifecycle.
• Work closely with verification teams to ensure quality component development and meet design specifications.
• Work closely with Physical design teams to ensure quality PPA (Power, Performance, Area) targets are achieved.
• Provide post silicon support to ensure successful bring up and troubleshoot any hardware issues.

Experience Required: 12+ years of experience in RTL Design with excellent foundation in fabric/transport architecture and coherency. Experience in memory design and cache design is required.

Education: Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Key Skills

Education

Any Graduate