Description

You will lead SOC and block-level physical design activities for high-performance, low-power designs.

Responsibilities

• Execute SOC and block-level P&R activities from floorplanning through routing.
• Manage timing closure and physical design tasks including IO pad-ring, power planning, placement, CTS, and extraction.
• Address design challenges related to performance, power, signal integrity, IR drop, and manufacturability.
• Oversee physical verification tasks such as LVS, DRC, and other electrical checks.
• Lead junior team members and assess architectural limitations from a physical design perspective.

Required Skills

• 4 to 7 years of relevant experience in physical design.
• Proven track record of at least one full chip tape-out.
• Hands-on expertise in deep sub-micron design processes (65/45/40/28/14/10nm).
• Technical proficiency in PNR, STA, and EMIR.
• Deep knowledge of floorplanning, CTS, routing, and noise reduction/crosstalk.
• Experience with physical verification including LVS and DRC.
• Ability to manage schedules, task volumes, and personnel requirements.

Key Skills

Education

Not specified