Description

Lead SOC and block-level physical design for high-performance, low-power chips, owning the flow from floorplanning through final routing and sign-off.

Execute SOC and block-level place-and-route, including floorplanning, placement, CTS, and routing. Drive timing closure and manage physical design tasks for IO pad-rings and power planning. Solve design challenges related to performance, power, signal integrity, IR drop, and manufacturability. Oversee physical verification activities including LVS, DRC, and other electrical checks. Lead junior team members and evaluate architectural limitations from a physical design perspective.

Required Skills

• 4+ years of experience in physical design with at least one full chip tape-out.
• Hands-on expertise in deep sub-micron processes (65/45/40/28/14/10nm).
• Proficiency in PNR, STA, and EMIR tools.
• Deep knowledge of floorplanning, CTS, routing, and noise reduction/crosstalk.
• Experience with physical verification flows including LVS and DRC.
• Ability to manage schedules, task volumes, and personnel requirements.
• Proficiency in TCL scripting.

Key Skills

Education

Not specified