Description

You will execute full-cycle digital IC design from floorplanning through to tape-out.

Responsibilities

• Execute floorplanning, placement, routing, and clock tree synthesis (CTS).
• Optimize designs for power, performance, and area (PPAs).
• Conduct DRC, LVS, and parasitic extraction to ensure design sign-off.
• Drive the tape-out process and collaborate with design, verification, and manufacturing teams.
• Perform static timing analysis (STA) to ensure timing closure.

Required Skills

• 5+ years of experience in digital IC design.
• Proficiency with Innovus, ICC2, and Fusion Compiler for place and route.
• Hands-on experience with 7nm, 5nm, or lower process nodes.
• Expertise in floorplanning, placement, routing, and CTS.
• Experience with timing closure and static timing analysis (STA).
• Ability to perform DRC, LVS, and parasitic extraction.
• Proficiency in scripting with TCL, Perl, or Python for design automation.
• Bachelor’s or Master’s degree in Electrical Engineering or any graduate degree.

Preferred Skills

• Experience with DFM, DFT, and advanced packaging technologies.

Key Skills

Education

Any Graduate