Description

Lead backend implementation for complex SoC environments, owning synthesis, timing closure, and power analysis.

Responsibilities

• Run logic and physical synthesis to generate optimized gate-level netlists for timing, area, and power.
• Debug timing, area, and congestion issues while collaborating with RTL and physical designers on resolutions.
• Perform power estimation at RTL and gate levels to identify reduction opportunities.
• Develop timing constraints for RTL synthesis and PrimeTime-STA at both block and SoC levels.
• Create automation scripts and methodologies for FE-tools including Lint, CDC, RDC, synthesis, STA, and power.

Required Skills

• 10+ years of experience in backend implementation, synthesis, and timing closure.
• Expertise in power analysis using PTPX.
• Experience with RTL synthesis and design optimization for PPA (Power, Performance, Area).
• Proficiency in scripting languages such as Python and TCL for building EDA tool flows.
• Hands-on experience with RTL Lint and working with designers on waivers.
• Ability to analyze inter-block timing and define IO budgets for partition blocks.
• Knowledge of CDC (Clock Domain Crossing).
• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.

Key Skills

Education

ANY GRADUATE