Description

You will own full-chip static timing analysis and timing closure for complex designs.

This role is on-site.

Responsibilities

• Execute full-chip Static Timing Analysis (STA) and manage SDC construction.
• Drive timing closure through close collaboration with the design team.
• Implement DMSA/Tweaker ECO flows to resolve timing violations.
• Perform detailed timing analysis to ensure design integrity.

Required Skills

• 4+ years of experience in Physical Design and STA.
• Expertise in full-chip STA and SDC construction.
• Practical experience with DMSA/Tweaker ECO flows.
• Strong proficiency in timing analysis and closure methodologies.
• Background in Physical Design workflows.
• Ability to work within a collaborative engineering team.

Preferred Skills

• Experience with advanced node processes.

Key Skills

Education

Any Graduate