Description

You will own complex RTL design modules for networking products, taking them from concept to silicon.

This role is hybrid.

Responsibilities

• Design and implement complex RTL modules using Verilog for networking products.
• Manage the full lifecycle of design modules from concept through to silicon implementation.
• Develop and maintain scripting tools using Perl, CSH, AWK, and SED.
• Collaborate with the team to resolve OS-silicon interactions and optimize memory subsystems.
• Drive innovation by creating new ideas and pursuing patents.

Required Skills

• 10+ years of experience in RTL design for networking products.
• Proficiency in Verilog for RTL design.
• Strong scripting skills in Perl, CSH, AWK, and SED.
• Experience with RDMA, TCP/IP, or UDP protocols.
• Understanding of OS-silicon interactions, scatter-gather engines, and programmable packet parsers.
• Masters degree in Engineering or related field preferred.

Preferred Skills

• Exposure to memory subsystem design and optimization.
• Track record of filing patents or creating new design ideas.

Key Skills

Education

Not specified