Description

You will design and implement complex digital circuits at the Register Transfer Level (RTL) for ASIC projects.

Responsibilities

• Create and optimize RTL designs using Verilog or VHDL to meet performance goals and design constraints.
• Contribute to the architectural and microarchitectural definition of ASIC projects in collaboration with system architects and verification engineers.
• Develop test plans and execute RTL verification activities including simulation, formal verification, and linting.
• Guide the synthesis process and work with Physical Design teams to achieve timing closure and optimize for area, power, and performance.
• Maintain design documentation, including specifications, constraints, and integration guidelines.

Required Skills

• At least 4 years of industry experience in ASIC RTL design and verification.
• Proficiency in Verilog or VHDL for RTL design.
• Strong understanding of the full ASIC design flow, including synthesis and timing closure.
• Experience with simulation-based verification and formal verification techniques.
• Proficiency in scripting languages such as Python or Tcl.
• Experience with programming languages like C or C++ for design automation and modeling.
• Familiarity with industry-standard EDA tools for synthesis, simulation, and timing analysis.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Skills

• Experience with SystemVerilog and UVM.
• Experience with FPGA prototyping.

Key Skills

Education

Any Graduate