Description

You will own low-power RTL design and microarchitecture development. You execute synthesis and timing closure while optimizing for area and power reduction. You perform low-power estimation throughout the design cycle.

Responsibilities

• Develop low-power RTL designs and define microarchitecture.
• Execute synthesis and timing closure processes.
• Optimize microarchitecture and RTL for area and power reduction.
• Perform low-power estimation throughout the design cycle.

Required Skills

• 5+ years of experience in RTL design.
• Proficiency in Verilog.
• Experience with ASIC design tools including VCS, Verdi, and Design Compiler.
• Knowledge of power estimation tools such as Spyglass or PTPX.
• Proficiency in scripting languages including Shell, Perl, or Python.
• Experience with Application-Specific Integrated Circuits (ASIC).
• Solid understanding of Microarchitecture and Hardware Architecture.

Preferred Skills

• Experience with Arithmetic units or Floating point datapath design.
• Hardware architecture exploration and performance modelling.
• C programming language, Machine Learning/AI domain, or DRAM Memory controller experience.

Key Skills

Education

Any Graduate