Description

Key Skills: Verilog, SoC Design, RTL Design, Physical Design, Microarchitecture, Perl Scripting, Shell Scripting, CDC, LINT, Verification

Good to Have Skills: Understanding of SoC topology networks, clocking and reset design, IO design, fuse mapping, VCLP connectivity checks, debugging skills for verification issues, experience with server SoC integration, and knowledge of DFT design collaboration.

Roles & Responsibilities:

• Work with SoC Architects and IP Design Teams to define microarchitecture including clocking, reset, IO, and fuse implementation.
• Implement SoC design features and blocks while owning connectivity across various IP components.
• Collaborate with Physical Design Team to deliver collaterals required for PD and implement SoC topology networks.
• Own and drive RTL Quality checks and audits including Lint, CDC, VCLP, and connectivity verification.
• Work closely with architecture, IP design, Physical Design teams, and DFT Design teams to achieve first pass silicon success.

Experience Required: 12+ years of experience in SoC Integration activities and definition of microarchitecture. Strong understanding of SoC Design aspects including clocking, IO, latency, reset, fuse map, and SoC topology networks. Experience with triaging and debugging issues reported by verification teams.

Education: Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Key Skills

Education

Any Graduate