Description

Define and implement SoC microarchitecture, owning connectivity across IP components and driving RTL quality through rigorous verification.

This role is on-site.

Responsibilities

• Define microarchitecture including clocking, reset, IO, and fuse implementation alongside SoC Architects and IP Design Teams.
• Implement SoC design features and blocks while owning connectivity across various IP components.
• Collaborate with Physical Design teams to deliver collaterals and implement SoC topology networks.
• Own and drive RTL quality checks and audits, including Lint, CDC, VCLP, and connectivity verification.
• Triage and debug issues reported by verification teams to achieve first-pass silicon success.

Required Skills

• 12+ years of experience in SoC integration activities and microarchitecture definition.
• Strong proficiency in Verilog, RTL Design, and SoC Design.
• Experience with Physical Design collaboration and understanding of SoC topology networks.
• Knowledge of Microarchitecture, clocking, reset, IO, latency, and fuse mapping.
• Proficiency in Perl Scripting and Shell Scripting.
• Experience with CDC, Lint, and VCLP connectivity checks.
• Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

Preferred Skills

• Understanding of DFT design collaboration and debugging skills for verification issues.
• Experience with server SoC integration.

Key Skills

Education

Any Graduate