Description

You will design and build complex hardware simulation environments for SoC validation.

Responsibilities

• Design and develop SystemC TLM models representing SoC architecture, including processors, DSPs, NoC, DMA, and memory controllers.
• Integrate first-party and vendor models into the Virtual Platform, creating automated workflows for register-level accuracy and SoC connectivity.
• Collaborate with architects and designers to develop high-fidelity, fast C++ models for first-party IP.
• Coordinate virtual platforms with hardware programs, validating SoCs and architectural changes using system software and firmware.
• Instrument models to enable SoC and system architecture exploration, tracking power and performance metrics.

Required Skills

• 10+ years of experience, with 5+ years in hardware model simulation or virtual platform development for complex SoCs.
• High proficiency in modern C++ for chip-design or simulation.
• Experience with the SystemC/TLM library.
• Experience with virtual platform tools like Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models.
• Familiarity with processor/DSP architectures (ARM, RISC-V, XTensa).
• Familiarity with NoC, MMU, address translations, and cache modeling.
• Proficiency in Python for automating design flows and collateral data creation.
• Familiarity with C++ concurrency support (threads, atomic operations, memory ordering).

Key Skills

Education

Any Gradute