Description

You will architect, implement, and validate Design for Test (DFT) techniques for test-chips and hard-macros in SoC-style designs.

Responsibilities

• Architect and implement DFT logic at the RTL and synthesis gate levels.
• Generate ATPG-targeted test patterns for silicon execution and validate functionality.
• Collaborate with RTL, Verification, Physical Implementation, and STA teams to ensure timing closure and successful tape-out.
• Partner with Test and Debug teams on silicon characterization and validation.

Required Skills

• 5+ years of proven experience in Design for Test (DFT).
• Proficiency in Verilog RTL coding.
• Hands-on expertise with scan compression, Memory BIST, and Logic BIST.
• Proficiency in JTAG/IJTAG and at-speed testing.
• Experience with ATPG, fault simulation, and back-annotated gate-level verification.
• Strong working knowledge of Unix/Linux environments.
• Experience with silicon debug and Siemens, Cadence, or Synopsys DFT and simulation tools.

Preferred Skills

• Familiarity with IEEE 1149, 1500, and 1687 standards.
• Knowledge of Synthesis and Static Timing Analysis (STA).

Key Skills

Education

Any Graduate