Description

You will lead logic verification efforts to enable tapeout for control ASICs.

Responsibilities

• Create verification plans based on IP design specifications.
• Build standalone IP test benches using SystemVerilog.
• Develop test cases, coverage models, and assertions to ensure functional correctness.
• Generate functional and code coverage metrics and collaborate with developers on IP functionality.
• Deliver functional test vectors for post-silicon validation.

Required Skills

• 8+ years of hands-on experience in Logic IP Verification using SystemVerilog.
• Experience with UVM and SystemVerilog logic verification environments.
• Hands-on experience verifying ARM Cortex M4 based subsystems or SOCs.
• Experience with debug interfaces such as SWD and SWJ.
• Knowledge of ARM microcontroller architecture and debug infrastructure.
• Experience verifying silicon IPs such as UART, CAN-FD, I2C, SPI, QSPI, SD/UMMC, or General purpose timers/PWM.
• Ability to perform C-based and SystemVerilog based IP verification.
• Strong problem-solving and written/verbal communication skills.

Preferred Skills

• Knowledge of cryptography algorithms and data encryption/decryption verification.

Key Skills

Education

Any Graduate