Description

You will own ASIC verification for graphics processor IP components, building directed and random tests using UVM and SystemVerilog. Debug test failures to determine root causes and collaborate with RTL and firmware engineers to resolve design defects.

This role is on-site.

Responsibilities

• Build directed and random verification tests for graphics processor IP components using UVM and SystemVerilog.
• Debug test failures to determine root causes and collaborate with RTL and firmware engineers to resolve design defects.
• Develop test plan documentation accounting for hardware, firmware, and software driver interactions.
• Estimate effort for new feature tests and modify the test environment as required.
• Review functional and code coverage metrics to ensure completeness and add tests to meet requirements.

Required Skills

• 5+ years of IP-level ASIC verification experience.
• Proficiency in UVM testbench development.
• Strong knowledge of SystemVerilog, Verilog, and RTL design.
• Experience with C++ and C programming for verification environments.
• Ability to debug firmware and RTL code using simulation tools in Linux and Windows.
• Familiarity with graphics pipeline architecture and SystemC.
• Experience with Perl scripting.

Preferred Skills

• TLM experience and automation in distributed compute environments.
• Knowledge of video codec systems, multimedia solutions, or HLS tools.
• Leadership experience and capabilities for mentorship.

Key Skills

Education

Any Graduate