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Senior Verification Engineer

Hays

 

Cambridge, United Kingdom

Posted On: 30+ days ago
Experience: 5+ years
Availability: Onsite
Openings: 1
Category: Verification Engineer
Tenure: No Preference/Any
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Description

Integrate machine learning technologies into hardware verification workflows to drive data-driven decision making and improve efficiency.

This role is on-site.

Responsibilities

  • Embed ML4V technologies into testbenches and production environments to optimize workflows and test generation.
  • Collaborate with data scientists to extract testbench data for improving machine learning models.
  • Debug ML4V issues in partnership with Engineering and DevOps teams to ensure service continuity.
  • Evaluate emerging ML technologies from internal teams and EDA partners.
  • Report on user experience and project requirements to inform the ML4V roadmap.

Required Skills

  • 5+ years of experience in hardware verification.
  • Proficiency in System Verilog and UVM.
  • Experience developing coverage-driven constrained-random verification environments.
  • Experience managing all stages of the verification lifecycle for complex IP.
  • Proficiency in Python or other interpreted scripting languages.
  • Experience with shell scripting.

Preferred Skills

  • Experience with C/C++.
  • Proficiency with EDA simulation, debug, and coverage tools in batch workflows.
  • Understanding of machine-readable formats like JSON.

Education

Any Graduate

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