Description

You will lead RTL and firmware development for high-speed LPDDR and DDR IPs, owning the design lifecycle from pathfinding through physical implementation.

Responsibilities

• Execute RTL design for memory I/O and digital architecture development.
• Develop PHY link layer designs and perform Analog/Digital co-design with architects.
• Manage timing synthesis to drive physical implementation of digital designs.
• Collaborate with architecture, hardware, and firmware teams to define and verify new features.
• Build unit tests and debug design failures to identify root causes alongside DV and firmware engineers.

Required Skills

• 5 years of experience in silicon design or related fields.
• Hands-on expertise with RTL development and coding.
• Deep knowledge of LPDDR and DDR IPs.
• Experience with firmware (FW) development.
• Strong understanding of circuit design and digital architecture.
• Ability to perform timing synthesis and drive physical implementation.
• Experience with PHY link layer design and verification.
• Strong analytical skills for debugging design defects and root cause analysis.

Key Skills

Education

THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: • RTL design for memory I/O • PHY Digital Architecture development from pathfinding, coding, verification to physical implementation • PHY link layer design, implementation & verification with Analog and System architect. • PHY Analog/Digital co-design • Digital design and RTL coding • Timing Synthesis & Drive Physical implementation • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified • Estimate the time required to write the new feature tests and any required changes to the test environment • Build the unit tests • Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues