Description

Senior Verification Engineer responsible for block and SoC level validation.

Responsibilities

• Review architecture specs and author test plans to ensure complete coverage.
• Develop UVM testbenches from scratch, including sequences, scoreboards, and coverage models.
• Implement DPI calls for C reference models to verify design functionality.
• Build UVM agents with monitors, drivers, and assertions.
• Debug block and SoC level issues independently.

Required Skills

• 15-20 years of experience in silicon verification.
• Deep expertise in UVM methodology and OOP.
• Experience verifying SoCs with AMBA protocols.
• Strong skills in test plan creation and review.
• Ability to work independently with minimal supervision.

Key Skills

Education

Any Graduate