Description

Key Responsibilities

Design and integrate ARM-based subsystems using Arm Corestone reference packages.

Develop and modify RTL for CPU subsystems, AMBA interconnects, memory controllers, and peripheral IPs.

Collaborate with architecture teams on microarchitecture updates and performance optimization.

Work with verification teams on functional debugging and coverage closure.

Support synthesis, Static Timing Analysis (STA), CDC/RDC checks, and physical design activities.

Support emulation, FPGA prototyping, and early silicon bring-up.

Participate in design reviews, documentation, and methodology improvements.

Required Skills

7–11 years of experience in SoC / ASIC / Subsystem Design.

Strong knowledge of ARM Architecture.

Hands-on experience with Arm Corestone or similar ARM reference designs.

Strong RTL design and ASIC front-end integration experience.

Good knowledge of AMBA protocols: AXI, AHB, and APB.

Experience with ASIC synthesis, CDC, and RDC.

Experience with Cadence tools for CDC/RDC, synthesis, and timing analysis.

Strong Static Timing Analysis (STA) knowledge.

Experience with simulation, lint, RTL debugging, and front-end design flows.

Knowledge of UPF / low-power design is an advantage.

FPGA prototyping, emulation, or early silicon bring-up experience is a plus.

Exposure to AI/ML accelerator-based SoCs is an added advantage

Key Skills

Education

Any Gradute