Description

You will own the end-to-end verification lifecycle for SoC designs.

Responsibilities

• Develop comprehensive test plans and build verification environments to achieve code and functional coverage goals.
• Execute verification plans by developing C/C++ test cases and SystemVerilog/UVM testbench components.
• Integrate 3rd party VIP components and report verification results.
• Collaborate with stakeholders to define SoC verification strategies and align on functional and safety-related requirements.
• Lead technical efforts in Digital/Analog-Mixed Signal verification, including exploring new methodologies and environments.

Required Skills

• 5+ years of relevant work experience in SoC verification.
• Hands-on experience with SystemVerilog and UVM.
• Proficiency in C/C++.
• Experience with Xcelium, Spectre(X), and Simvision tools.
• Strong foundational knowledge of digital and mixed-signal design and verification.
• Experience with version control systems such as Git/Bitbucket, ClearCase, CVS, or SVN.
• Knowledge of bug management schemes.
• Bachelor's or Master's degree in Electrical Engineering or Computer Science.

Preferred Skills

• Experience with ADC and mixed-signal verification.

Key Skills

Education

Any Graduate