Description

You will execute SoC verification tasks and collaborate with stakeholders to define verification strategies and plans.

Responsibilities

• Review and interpret functional and safety-related requirements.
• Develop C/C++ test cases and SystemVerilog/UVM testbench components.
• Integrate 3rd party VIP components into the verification environment.
• Align with stakeholders to identify and execute verification plans.

Required Skills

• 5+ years of relevant experience in SoC verification.
• Hands-on experience with SystemVerilog and UVM.
• Proficiency in C and C++.
• Experience using Xcelium, Spectre(X), and Simvision tools.
• Strong foundational knowledge of digital and mixed-signal design and verification.
• Experience with version control tools such as Git, Bitbucket, ClearCase, CVS, or SVN.
• Experience with bug management schemes.
• Bachelor's or Master's degree in Electrical Engineering or Computer Science.

Key Skills

Education

Any Graduate