Description

You will own the verification process for System-on-Chip (SoC) designs.

Responsibilities

• Define and implement SoC verification plans, building test benches for sub-system and SoC level verification.
• Develop functional tests according to the verification test plan.
• Drive Design Verification to closure using defined metrics for functional and code coverage.
• Debug, root-cause, and resolve functional failures by partnering with the Design team.
• Collaborate with Design, Model, Emulation, and Silicon validation teams to ensure design quality.

Required Skills

• 8 to 10 years of hands-on experience with SystemVerilog/UVM methodology.
• Track record of 'first-pass success' in ASIC development cycles.
• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• Proficiency in EDA tools and scripting using Python, TCL, Perl, or Shell to build verification flows.
• Experience with functional verification techniques like SV Assertions, Formal, or Emulation.
• Experience with version control systems such as Git.
• Familiarity with Synopsys or Cadence EDA Design/Verification tools.
• Experience with high-speed interface verification like PCIe, DDR, or Ethernet.

Key Skills

Education

Bachelor's degree