Description

You will own the performance modeling and architectural validation of System-on-Chip designs, projecting performance metrics and validating concepts before RTL freeze. This role is on-site.

Responsibilities

• Build and maintain execution-driven and trace-driven SoC performance simulators using C++, SystemC, or Python.
• Construct scalable models to evaluate CPU, GPU, and ML accelerator configurations under multi-master workloads.
• Profile industry-standard benchmarks and real-world use cases to identify system-wide bottlenecks.
• Analyze cache hierarchies, memory controllers, NoC topologies, and routing algorithms to optimize bandwidth and latency.
• Capture and manipulate instruction and memory traces from pre-silicon environments and post-silicon hardware.

Required Skills

• 5+ years of industry experience in SoC or processor architecture and performance modeling.
• Proficiency in C++, Python, and SystemC for simulation and modeling.
• Deep understanding of computer architecture, SoC architecture, and cache coherence protocols.
• Experience with performance modeling tools such as gem5.
• Knowledge of virtual memory systems and hardware subsystem interactions.
• BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related field.

Preferred Skills

• Experience with post-silicon debug tools and hardware performance counters (ARM PMU, Intel VTune).
• Familiarity with ML frameworks, PyTorch, TensorFlow, and data visualization tools.

Key Skills

Education

Any Graduate